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ble-dongle: Prevent disable of HSI48 osc used for USB

ble
Andreas Berthoud 4 years ago
parent
50e08983c5
commit
8c64cef923
1 changed files with 175 additions and 6 deletions
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  1. 181
      nucleo-wb55-dongle-ble/Core/Src/main.c

181
nucleo-wb55-dongle-ble/Core/Src/main.c
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@ -27,6 +27,12 @@
#include "stm32_seq.h"
#include "commands.h"
#include "stm32_lpm.h"
#include "stm32_seq.h"
#include "dbg_trace.h"
#include "hw_conf.h"
#include "otp.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@ -57,7 +63,11 @@ static void MX_GPIO_Init(void);
static void MX_RF_Init(void);
static void MX_RTC_Init(void);
/* USER CODE BEGIN PFP */
void PeriphClock_Config(void);
static void Reset_Device( void );
static void Reset_IPCC( void );
static void Reset_BackupDomain( void );
static void Init_Exti( void );
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
@ -81,14 +91,15 @@ int main(void)
HAL_Init();
/* USER CODE BEGIN Init */
Reset_Device();
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
PeriphClock_Config();
Init_Exti(); /**< Configure the system Power Mode */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
@ -98,7 +109,7 @@ int main(void)
MX_RTC_Init();
/* USER CODE BEGIN 2 */
int counter_value = 0;
//int counter_value = 0;
/* USER CODE END 2 */
/* Init code for STM32_WPAN */
@ -112,8 +123,7 @@ int main(void)
HAL_GPIO_WritePin(LED_GREEN_GPIO_Port, LED_GREEN_Pin, GPIO_PIN_RESET);
HAL_Delay(20);
// UTIL_SEQ_Run(~0);
UTIL_SEQ_Run(UTIL_SEQ_DEFAULT);
pop_and_execute_commands();
// HAL_Delay(450);
@ -290,6 +300,165 @@ static void MX_GPIO_Init(void)
}
/* USER CODE BEGIN 4 */
void PeriphClock_Config(void)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
RCC_CRSInitTypeDef RCC_CRSInitStruct = { 0 };
/**
* This prevents the CPU2 to disable the HSI48 oscillator when
* it does not use anymore the RNG IP
*/
LL_HSEM_1StepLock( HSEM, 5 );
LL_RCC_HSI48_Enable();
while(!LL_RCC_HSI48_IsReady());
/* Select HSI48 as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
/*Configure the clock recovery system (CRS)**********************************/
/* Enable CRS Clock */
__HAL_RCC_CRS_CLK_ENABLE();
/* Default Synchro Signal division factor (not divided) */
RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
/* HSI48 is synchronized with USB SOF at 1KHz rate */
RCC_CRSInitStruct.ReloadValue = RCC_CRS_RELOADVALUE_DEFAULT;
RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
/* Set the TRIM[5:0] to the default value*/
RCC_CRSInitStruct.HSI48CalibrationValue = RCC_CRS_HSI48CALIBRATION_DEFAULT;
/* Start automatic synchronization */
HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
return;
}
/*************************************************************
*
* LOCAL FUNCTIONS
*
*************************************************************/
static void Reset_Device( void )
{
#if ( CFG_HW_RESET_BY_FW == 1 )
Reset_BackupDomain();
Reset_IPCC();
#endif
return;
}
static void Reset_IPCC( void )
{
LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
LL_C1_IPCC_ClearFlag_CHx(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_ClearFlag_CHx(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C1_IPCC_DisableTransmitChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_DisableTransmitChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C1_IPCC_DisableReceiveChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_DisableReceiveChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
return;
}
static void Reset_BackupDomain( void )
{
if ((LL_RCC_IsActiveFlag_PINRST() != FALSE) && (LL_RCC_IsActiveFlag_SFTRST() == FALSE))
{
HAL_PWR_EnableBkUpAccess(); /**< Enable access to the RTC registers */
/**
* Write twice the value to flush the APB-AHB bridge
* This bit shall be written in the register before writing the next one
*/
HAL_PWR_EnableBkUpAccess();
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
}
return;
}
static void Init_Exti( void )
{
/**< Disable all wakeup interrupt on CPU1 except IPCC(36), HSEM(38) */
LL_EXTI_DisableIT_0_31(~0);
LL_EXTI_DisableIT_32_63( (~0) & (~(LL_EXTI_LINE_36 | LL_EXTI_LINE_38)) );
return;
}
/*************************************************************
*
* WRAP FUNCTIONS
*
*************************************************************/
void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait += HAL_GetTickFreq();
}
while ((HAL_GetTick() - tickstart) < wait)
{
/************************************************************************************
* ENTER SLEEP MODE
***********************************************************************************/
LL_LPM_EnableSleep( ); /**< Clear SLEEPDEEP bit of Cortex System Control Register */
/**
* This option is used to ensure that store operations are completed
*/
#if defined ( __CC_ARM)
__force_stores();
#endif
__WFI( );
}
}
/* USER CODE END 4 */
/**

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